/*
 ***************************************************************************
 * MediaTek Inc. 
 *
 * All rights reserved. source code is an unpublished work and the
 * use of a copyright notice does not imply otherwise. This source code
 * contains confidential trade secret material of MediaTek. Any attemp
 * or participation in deciphering, decoding, reverse engineering or in any
 * way altering the source code is stricitly prohibited, unless the prior
 * written consent of MediaTek, Inc. is obtained.
 ***************************************************************************

	Module Name:
	mt_tx_pwr.h
*/
#ifndef __MT_TX_PWR_H__
#define __MT_TX_PWR_H__

#define POWER_UP_CATEGORY_RATE_NUM         7

typedef struct MT_TX_PWR_CAP {
#define INTERNAL_PA 0
#define EXTERNAL_PA 1
	UINT8 pa_type;
#define TSSI_TRIGGER_STAGE 0
#define TSSI_COMP_STAGE 1
#define TSSI_CAL_STAGE 2
	UINT8 tssi_stage;
#define TSSI_0_SLOPE_G_BAND_DEFAULT_VALUE 0x84
#define TSSI_1_SLOPE_G_BAND_DEFAULT_VALUE 0x83
	UINT8 tssi_0_slope_g_band;
	UINT8 tssi_1_slope_g_band;
#define TSSI_0_OFFSET_G_BAND_DEFAULT_VALUE 0x0A
#define TSSI_1_OFFSET_G_BAND_DEFAULT_VALUE 0x0B
	UINT8 tssi_0_offset_g_band;
	UINT8 tssi_1_offset_g_band;
#define TX_TARGET_PWR_DEFAULT_VALUE 0x26
	CHAR tx_0_target_pwr_g_band;
	CHAR tx_1_target_pwr_g_band;
	CHAR tx_0_chl_pwr_delta_g_band[3];
	CHAR tx_1_chl_pwr_delta_g_band[3];
	CHAR delta_tx_pwr_bw40_g_band;

	CHAR tx_pwr_cck_1_2;
	CHAR tx_pwr_cck_5_11;
	CHAR tx_pwr_g_band_ofdm_6_9;
	CHAR tx_pwr_g_band_ofdm_12_18;
	CHAR tx_pwr_g_band_ofdm_24_36;
	CHAR tx_pwr_g_band_ofdm_48;
	CHAR tx_pwr_g_band_ofdm_54;
	CHAR tx_pwr_ht_bpsk_mcs_0_8;
	CHAR tx_pwr_ht_bpsk_mcs_32;
	CHAR tx_pwr_ht_qpsk_mcs_1_2_9_10;
	CHAR tx_pwr_ht_16qam_mcs_3_4_11_12;
	CHAR tx_pwr_ht_64qam_mcs_5_13;
	CHAR tx_pwr_ht_64qam_mcs_6_14;
	CHAR tx_pwr_ht_64qam_mcs_7_15;
}MT_TX_PWR_CAP_T;

typedef enum _POWER_ACTION_CATEGORY
{
    SKU_FEATURE_CTRL = 0x0,
    PERCENTAGE_FEATURE_CTRL = 0x1,
    PERCENTAGE_DROP_CTRL = 0x2,
    BF_POWER_BACKOFF_FEATURE_CTRL = 0x3,
    BF_TX_POWER_BACK_OFF = 0x4,
    RF_TXANT_CTRL = 0x5,
    ATEMODE_CTRL = 0x6,
    TX_POWER_SHOW_INFO = 0x7,
    TPC_FEATURE_CTRL = 0x8,
	MU_TX_POWER_CTRL = 0x9,
	BF_NDPA_TXD_CTRL = 0xa,
	TSSI_WORKAROUND = 0xb,
	THERMAL_MANUAL_CTRL = 0xc,
	THERMAL_COMPENSATION_CTRL = 0xd,
	TX_RATE_POWER_CTRL = 0xe,
	TXPOWER_UP_TABLE_CTRL = 0xf,
	POWER_ACTION_NUM
} POWER_ACTION_CATEGORY, *P_POWER_ACTION_CATEGORY;

typedef enum _TSSI_ACTION_CATEGORY
{
    EPA_STATUS = 0,
    TSSI_TRACKING_ENABLE = 1,
    FCBW_ENABLE = 2,
    TSSI_COMP_BACKUP = 3,
    TSSI_COMP_CONFIG = 4
} TSSI_ACTION_CATEGORY, *P_TSSI_ACTION_CATEGORY;

typedef enum _POWER_EVENT_CATEGORY
{
    TXPOWER_EVENT_SHOW_INFO = 0,
    TXPOWER_EVENT_UPDATE_COMPENSATE_TABLE = 1,
    TXPOWER_EVENT_UPDATE_EPA_STATUS = 2
} POWER_EVENT_CATEGORY, *P_POWER_EVENT_CATEGORY;

typedef enum _POWER_BOOST_TABLE_CATEGORY
{
    POWER_UP_CATE_CCK_OFDM = 0,
    POWER_UP_CATE_HT20,
    POWER_UP_CATE_HT40,
    POWER_UP_CATE_VHT20,
    POWER_UP_CATE_VHT40,
    POWER_UP_CATE_VHT80,
    POWER_UP_CATE_VHT160,
    POWER_UP_CATE_NUM
} POWER_BOOST_TABLE_CATEGORY, *P_POWER_BOOST_TABLE_CATEGORY;

typedef enum _POWER_RATE_POWER_CCK_CATEGORY
{
    RATE_POWER_CCK_1M2M = 0,
    RATE_POWER_CCK_5M11M,
    RATE_POWER_CCK_NUM
} POWER_RATE_POWER_CCK_CATEGORY, *P_POWER_RATE_POWER_CCK_CATEGORY;

typedef enum _POWER_RATE_POWER_OFDM_CATEGORY
{
    RATE_POWER_OFDM_6M9M = 0,
    RATE_POWER_OFDM_12M18M,
    RATE_POWER_OFDM_24M36M,
    RATE_POWER_OFDM_48M,
    RATE_POWER_OFDM_54M,
    RATE_POWER_OFDM_NUM
} POWER_RATE_POWER_OFDM_CATEGORY, *P_POWER_RATE_POWER_OFDM_CATEGORY;

typedef enum _POWER_RATE_POWER_HT20_CATEGORY
{
    RATE_POWER_HT20_MCS0 = 0,
	RATE_POWER_HT20_MCS32,
    RATE_POWER_HT20_MCS12,
    RATE_POWER_HT20_MCS34,
    RATE_POWER_HT20_MCS5,
    RATE_POWER_HT20_MCS6,
    RATE_POWER_HT20_MCS7,
    RATE_POWER_HT20_NUM
} POWER_RATE_POWER_HT20_CATEGORY, *P_POWER_RATE_POWER_HT20_CATEGORY;

typedef enum _POWER_RATE_POWER_HT40_CATEGORY
{
    RATE_POWER_HT40_MCS0 = 0,
	RATE_POWER_HT40_MCS32,
    RATE_POWER_HT40_MCS12,
    RATE_POWER_HT40_MCS34,
    RATE_POWER_HT40_MCS5,
    RATE_POWER_HT40_MCS6,
    RATE_POWER_HT40_MCS7,
    RATE_POWER_HT40_NUM
} POWER_RATE_POWER_HT40_CATEGORY, *P_POWER_RATE_POWER_HT40_CATEGORY;

typedef enum _POWER_RATE_POWER_VHT20_CATEGORY
{
    RATE_POWER_VHT20_MCS0 = 0,
    RATE_POWER_VHT20_MCS12,
    RATE_POWER_VHT20_MCS34,
    RATE_POWER_VHT20_MCS56,
    RATE_POWER_VHT20_MCS7,
    RATE_POWER_VHT20_MCS8,
    RATE_POWER_VHT20_MCS9,
    RATE_POWER_VHT20_NUM
} POWER_RATE_POWER_VHT20_CATEGORY, *P_POWER_RATE_POWER_VHT20_CATEGORY;

typedef enum _POWER_RATE_POWER_VHT40_CATEGORY
{
    RATE_POWER_VHT40_MCS0 = 0,
    RATE_POWER_VHT40_MCS12,
    RATE_POWER_VHT40_MCS34,
    RATE_POWER_VHT40_MCS56,
    RATE_POWER_VHT40_MCS7,
    RATE_POWER_VHT40_MCS8,
    RATE_POWER_VHT40_MCS9,
    RATE_POWER_VHT40_NUM
} POWER_RATE_POWER_VHT40_CATEGORY, *P_POWER_RATE_POWER_VHT40_CATEGORY;

typedef enum _POWER_RATE_POWER_VHT80_CATEGORY
{
    RATE_POWER_VHT80_MCS0 = 0,
    RATE_POWER_VHT80_MCS12,
    RATE_POWER_VHT80_MCS34,
    RATE_POWER_VHT80_MCS56,
    RATE_POWER_VHT80_MCS7,
    RATE_POWER_VHT80_MCS8,
    RATE_POWER_VHT80_MCS9,
    RATE_POWER_VHT80_NUM
} POWER_RATE_POWER_VHT80_CATEGORY, *P_POWER_RATE_POWER_VHT80_CATEGORY;

typedef enum _POWER_RATE_POWER_VHT160_CATEGORY
{
    RATE_POWER_VHT160_MCS0 = 0,
    RATE_POWER_VHT160_MCS12,
    RATE_POWER_VHT160_MCS34,
    RATE_POWER_VHT160_MCS56,
    RATE_POWER_VHT160_MCS7,
    RATE_POWER_VHT160_MCS8,
    RATE_POWER_VHT160_MCS9,
    RATE_POWER_VHT160_NUM
} POWER_RATE_POWER_VHT160_CATEGORY, *P_POWER_RATE_POWER_VHT160_CATEGORY;

typedef enum _POWER_RATE_POWER_BW_CATEGORY
{
    RATE_POWER_BW20 = 0,
    RATE_POWER_BW40,
    RATE_POWER_BW80,
    RATE_POWER_BW160,
    RATE_POWER_BW_NUM
} POWER_RATE_POWER_BW_CATEGORY, *P_POWER_RATE_POWER_BW_CATEGORY;

#endif

